1. Field of the Invention
The invention relates in general to the field of memories, and more particularly to a memory controller and an associated signal generating method.
2. Description of the Related Art
A memory controller, generally connected to a memory module, writes data into the memory module or reads data from the memory module. One of the most common memory modules is a double data rate (DDR) memory module.
FIG. 1A and FIG. 1B show a schematic diagram of a connection relationship and an eye diagram of control signals between a memory controller and a memory module, respectively. A memory controller 100 and a DDR memory module 110 are disposed on a printed circuit board (PCB). The control signals at least includes a clock signal (CLK1), an address signal (A), a command signal (CMD), and a bank control signal (BANK). The command signal (CMD) includes a write enable signal (WE), a row address strobe signal (RAS), and a column address strobe signal (CAS). The bank control signal (BANK) is present in form of bank control signals BANK[2:0] at 3 pins, and the address (A) signal is present in form of address signals A[15:0] at 16 pins.
The memory controller 100 utilizes the control signals to control and access the DDR memory module 110, e.g., to read and write data. The DDR memory module 110 latches data in the address signal (A), the command signal (CMD) and the bank control signal (BANK) according to a signal edge (e.g., a rising edge or a falling edge) of the clock signal (CLK1). Thus, the memory controller 100 needs to appropriately adjust the phase of the clock signal (CLK1), so that the DDR memory module 100 is allowed to successfully latch the data in all of the control signals according to the signal edge of the clock signal (CLK1). For illustration purposes, in the example in the description below, the rising edge of the clock signal (CLK1) is utilized to latch the signals.
As shown in FIG. 1B, a period of the clock signal (CLK1) is T, and periods of the address signal (A), the command signal (CMD) and the bank control signal (BANK) are also T. However, as driving capabilities of the control signals are different, latching intervals (or referred to as data effective ranges) of the control signals are smaller than T. Therefore, to prevent the control signals from latching these control signals outside the latching intervals and thus from causing errors, the memory controller 100 needs to adjust the rising edge of the clock signal (CLK1) to within the latching intervals of these control signals.
As shown in FIG. 1B, the rising edge of the clock signal (CLK1) is adjusted to the latching interval (Eye_cmd) of the command signal (CMD), the latching interval (Eye_bank) of the bank control signal (BANK), and the latching interval (Eye_addr) of the address signal (A). It is apparent that the latching intervals of the above signals are all smaller than T. More particularly, having a large number of signals, the address signal (A) has a smallest latching interval (Eye_addr).
As the access speed of dynamic random access memories (DRAMs) continue to increase, DDR2 modules have evolved to DDR3 modules. However, with the increasing speed of memory modules, signal quality is significantly lowered. On further account of variations of PCBs and different pins of the memory modules of different specifications, slight differences may exist in the time that control signals need to travel from the memory controller to the memory module, and the rising time and falling time when signals are changed may be increased. As a result, the latching intervals of the control signals become smaller.
FIG. 2A and FIG. 2B show a schematic diagram of a connection relationship and an eye diagram of control signals between a memory controller and two memory modules, respectively. When controlling two DDR memory modules 210 and 220 by a memory controller 200, a first clock signal (CLK1) connects to the first DDR memory module 210, and a second clock signal (CLK2) connects to the second DDR memory module 220. Further, the two DDR memory modules 210 and 220 share an address signal (A), a command signal (CMD), and a bank control signal (BANK). That is, the first DDR memory module 210 latches the data in the address signal (A), the command signal (CMD) and the bank control signal (BANK) according to the first clock signal (CLK1); the second DDR memory module 220 latches the data in the address signal (A), the command signal (CMD) and the bank control signal (BANK) according to the second clock signal (CLK2).
The memory controller 200 is required to drive a pin count that is twice of that of the memory in 1A. In addition, considering variations of PCBs and different pins of the two DRAMs, quality of the signals are further deteriorated. Such signal deterioration is particularly severe for the address signal (A). Compared to FIG. 1B, the latching intervals in FIG. 2B are even smaller, and particularly the latching interval (Eye_addr) of the address signal (A) is extremely small. That is, with the extremely small latching interval (Eye_addr) of the address signal (A), it is made even more challenging for the memory controller 200 to make adjustment to provide appropriate phases for the clock signals (CLK1) and (CLK2) that allow the two DDR memory modules 210 and 220 to successively latch the signals.
Under high-speed requirements, the quality of all of the signals cannot be easily qualified. Therefore, there is a need for a solution that overcomes the above issues.